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19-0850; Rev 0; 7/07
KIT ATION EVALU BLE AVAILA
2-Wire Interfaced Low-EMI Key Switch Controller/GPO
General Description Features
Optional Key Release Detection on All Keys Monitor Up to 64 Keys 1.62V to 3.6V Operation Autosleep and Autowake to Minimize Current Consumption Under 1A Sleep Current FIFO Queues Up to 16 Debounced Key Events Key Debounce Time User Configurable from 9ms to 40ms Low-EMI Design Uses Static Matrix Monitoring Hardware Interrupt at the FIFO Level or at the End of Definable Time Period Up to Seven Open-Drain Logic Outputs Available Capable of Driving LEDs 400kbps, 5.5V-Tolerant, 2-Wire Serial Interface Selectable 2-Wire, Serial-Bus Timeout Four I2C Address Choices Small, 24-Pin TQFN Package (3.5mm x 3.5mm)
MAX7359
The MAX7359 interfaced peripheral provides microprocessors with management of up to 64 key switches. Key codes are generated for each press and release of a key for easier implementation of multiple key entries. Key inputs are monitored statically, not dynamically, to ensure low-EMI operation. The switches can be metallic or resistive (carbon) with up to 5k of resistance. The MAX7359 features autosleep and autowake to further minimize the power consumption of the device. The autosleep feature puts the device in a low-power state (1A typ) after a sleep timeout period. The autowake feature configures the MAX7359 to return to normal operating mode from sleep upon a key press. The key controller debounces and maintains a FIFO of key-press and release events (including autorepeat, if enabled). An interrupt (INT) output can be configured to alert key presses either as they occur, or at maximum rate. Any of the column drivers (COL2/PORT2-COL7/PORT7) or the INT, if not used, can function as a general-purpose output (GPO). The MAX7359 is offered in a small 24-pin TQFN (3.5mm x 3.5mm) package for cell phones, pocket PCs, and other portable consumer electronic applications. The MAX7359 operates over the -40C to +85C temperature range.
I2C
Applications
Cell Phones PDAs Handheld Games Portable Consumer Electronics
PART MAX7359ETG+
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 24 TQFN-EP* (3.5mm x 3.5mm) PKG CODE T243A3-1
+Denotes a lead-free package.
Typical Application Circuit
INPUT 1.62V TO 3.6V VCC
*EP = Exposed paddle.
MAX7359
COL_
8 SWITCH ARRAY, UP TO 64 SWITCHES
8 ROW_ SCL SDA INT AD0 GND
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) VCC ..........................................................................-0.3V to +4V COL2/PORT2-COL7/PORT7 ....................................-0.3V to +4V SDA, SCL, AD0, INT .................................................-0.3V to +6V All Other Pins ..............................................-0.3V to (VCC + 0.3V) DC Current on COL2/PORT2-COL7/PORT7 ......................25mA GND Current .......................................................................80mA Continuous Power Dissipation (TA = +70C) 24-Pin TQFN (derate 15.4mW/C above +70C)..........1229mW Operating Temperature Range (TMIN to TMAX) .....-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 1.62V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 2.5V, TA = +25C.) (Notes 1, 2)
PARAMETER Operating Supply Voltage SYMBOL VCC All key switches open, oscillator running, COL2-COL7 configured as key switches Operating Supply Current ICC N keys pressed Sleep-Mode Supply Current POR POR Hysteresis Key-Switch Source Current Key-Switch Source Voltage Key-Switch Resistance Startup Time from Shutdown Output Low Voltage COL2/PORT2 to COL7/PORT7 INT Output Oscillator Frequency Serial Bus Timeout Input High Voltage SDA, SCL, AD0 Input Low Voltage SDA, SCL, AD0 Output Low Voltage SDA Input Leakage Current PORHYST IKEY VKEY RKEY tSTART VOLPORT VOLINT FOSC tOUT VIH VIL VOLPORT ISINK = 10mA VCC = 0 to 6V -1 With bus timeout enabled 10 0.7 x VCC 0.3 x VCC 0.4 +1 ISINK = 10mA ISINK = 10mA 64 40 Operating mode (Note 3) 2000 VCC rising ISL 1.0 42 20 0.42 35 0.55 5 2400 0.2 0.5 CONDITIONS MIN 1.62 25 (25 + 20 x N) 0.6 5 1.6 TYP MAX 3.60 60 A UNITS V
A V mV A V k s V V kHz ms V V V A
SERIAL-INTERFACE SPECIFICATIONS
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO
I2C TIMING CHARACTERISTICS
(VCC = 1.62V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 2.5V, TA = +25C.) (Notes 1, 2) (Figure 2)
PARAMETER Input Capacitance (SCL, SDA, AD0) SCL Serial-Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock Low Period SCL Clock High Period Rise Time of Both SDA and SCL Signals, Receiving Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line SYMBOL CIN fSCL tBUF tHD, STA tSU, STA tSU, STO tHD, DAT tSU, DAT tLOW tHIGH tR tF tF.TX tSP Cb (Notes 3, 4) (Notes 3, 4) (Notes 3, 6) (Notes 3, 7) (Note 3) (Note 5) 100 1.3 0.7 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 300 300 250 50 400 (Notes 3, 4) Bus timeout disabled 0 1.3 0.6 0.6 0.6 0.9 CONDITIONS MIN TYP MAX 10 400 UNITS pF kHz s s s s s ns s s ns ns ns ns pF
MAX7359
Note 1: Note 2: Note 3: Note 4: Note 5:
All parameters are tested at TA = +25C. Specifications over temperature are guaranteed by design. All digital inputs at VCC or GND. Guaranteed by design. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V. A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge. Note 6: ISINK 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V. Note 7: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
Typical Operating Characteristics
(VCC = 2.5V, TA = +25C, unless otherwise noted.)
GPO PORT OUTPUT LOW VOLTAGE vs. SINK CURRENT
MAX7359 toc01
GPO PORT OUTPUT LOW VOLTAGE vs. SINK CURRENT
MAX7359 toc02
GPO PORT OUTPUT LOW VOLTAGE vs. SINK CURRENT
VCC = +3.6V
MAX7359 toc03
300 VCC = +2.4V 250 TA = +85C 200 VOL (mV)
300 250 200 VOL (mV) 150 100
VCC = +3.0V
300 250 200 VOL (mV) 150 100
TA = +85C
TA = +85C
150 100 50 0 0 5 10 15 ISINK (mA) 20 25 30 TA = +25C
TA = -40C 50 0 0 5 10 15 ISINK (mA) 20 TA = +25C
TA = -40C 50 0 25 30 0 5 10 15 ISINK (mA) 20 TA = +25C
TA = -40C
25
30
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7359 toc04
KEY-SWITCH SOURCE CURRENT vs. SUPPLY VOLTAGE
COL0 = GND KEY-SWITCH SOURCE CURRENT (A) TA = +85C 21.5
MAX7359 toc05
SLEEP MODE SUPPLY CURRENT vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT (A)
MAX7359 toc06
40 AUTOSLEEP = OFF 35 SUPPLY CURRENT (A)
22.0
2.0
1.5
30
TA = +85C
21.0 TA = +25C 20.5
TA = -40C
1.0
25 TA = -40C TA = +25C 15 1.6 2.0 2.4 2.8 3.2 3.6 SUPPLY VOLTAGE (V)
0.5
20
20.0 1.6 2.0 2.4 2.8 3.2 3.6 SUPPLY VOLTAGE (V)
0 1.6 2.1 2.6 3.1 3.6 SUPPLY VOLTAGE (V)
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO
Functional Block Diagram
MAX7359
MAX7359
64kHz OSCILLATOR
COLUMN ENABLE GPO ENABLE CURRENT DETECT CURRENT SOURCE COLUMN DRIVES
INT SDA SCL I2C INTERFACE CONTROL REGISTERS FIFO KEY SCAN
CL0 CL1 CL2* CL3* CL4* CL5* CL6* CL7* RO0 RO1 RO2 RO3 RO4 RO5 RO6 RO7
ROW ENABLE BUS TIMEOUT POR
OPENDRAIN ROW DRIVES
*GPO
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -- NAME ROW2 ROW3 COL3/PORT3 COL4/PORT4 ROW4 ROW5 ROW6 ROW7 COL6/PORT6 COL5/PORT5 COL2/PORT2 COL1 COL0 I.C. GND AD0 SDA SCL INT VCC N.C. COL7/PORT7 ROW0 ROW1 EP FUNCTION Row Input from Key Matrix. Leave ROW2 unconnected or connect to GND if unused. Row Input from Key Matrix. Leave ROW3 unconnected or connect to GND if unused. Column Output to Key Matrix or GPO. Leave COL3/PORT3 unconnected if unused. Column Output to Key Matrix or GPO. Leave COL4/PORT4 unconnected if unused. Row Input from Key Matrix. Leave ROW4 unconnected or connect to GND if unused. Row Input from Key Matrix. Leave ROW5 unconnected or connect to GND if unused. Row Input from Key Matrix. Leave ROW6 unconnected or connect to GND if unused. Row Input from Key Matrix. Leave ROW7 unconnected or connect to GND if unused. Column Output to Key Matrix or GPO. Leave COL6/PORT6 unconnected if unused. Column Output to Key Matrix or GPO. Leave COL5/PORT5 unconnected if unused. Column Output to Key Matrix or GPO. Leave COL2/PORT2 unconnected if unused. Column Output to Key Matrix. Leave COL1 unconnected if unused. Column Output to Key Matrix. Leave COL0 unconnected if unused. Internally Connected. Connect to GND for normal operation. Ground Adddress Input. ADO selects up to four device slave addresses (Table 10). I2C-Compatible, Serial-Data I/O I2C-Compatible, Serial-Clock Input Active-Low Interrupt Output. INT is open drain. Positive Supply Voltage. Bypass VCC to GND with a 0.047F or higher ceramic capacitor. No Connection. Not internally connected. Column Output to Key Matrix or GPO. Leave COL7/PORT7 unconnected is unused. Row Input from Key Matrix. Leave ROW0 unconnected or connect to GND if unused. Row Input from Key Matrix. Leave ROW1 unconnected or connect to GND if unused. Exposed Paddle. EP internally is connected to GND. Connect EP to a ground plane to increase thermal performance.
Detailed Description
The MAX7359 is a microprocessor peripheral low-noise key-switch controller that monitors up to 64 key switches with optional autorepeat, and key events are presented in a 16-byte FIFO. Key-switch functionality can be traded to provide up to six open-drain logic outputs. The MAX7359 features an automatic sleep mode and automatic wakeup that further reduce supply current consumption. The MAX7359 can be configured to enter sleep mode after a programmable time following a key event. The FIFO content is maintained during sleep mode and can be read in sleep mode. The MAX7359 does not enter autosleep when a key is held down. The autowake feature takes the MAX7359 out of sleep mode following a key-press event. Autosleep and autowake can be disabled.
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Interrupt requests can be configured to be issued on a programmable number of FIFO entries, or can be set to a period of time to prevent overloading the microprocessor with too many interrupts. The key-switch status can be checked at any time by reading the key-switch FIFO. A 1-byte read access returns both the next key-event in the FIFO (if there is one) and the FIFO status, so it is easy to operate the MAX7359 by polling. If the INT pin is not required, it can be configured as an open-drain general-purpose output (GPO) capable of driving an LED. If the application requires fewer keys to be scanned, up to six of the key-switch outputs can be configured as open-drain GPOs capable of driving LEDs. For each key-switch output used as a GPO, the number of key switches that can be scanned is reduced by eight.
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO
Key-Scan Controller
Key inputs are scanned statically, not dynamically, to ensure low-EMI operation. As inputs only toggle in response to switch changes, the key matrix can be routed closer to sensitive circuit nodes. The key controller debounces and maintains a FIFO of key-press and release events (including autorepeated key presses, if autorepeat is enabled). Table 1 shows keys order. D5 denote which of the 64 keys have been debounced and the keys are numbered as in Table 1. D7 indicates if there is more data in the FIFO except when D5:D0 indicate key 63 or key 62. When D5:D0 indicate key 63 or key 62, the host should read one more time to determine whether there is more data in FIFO. It is better to use key 62 and key 63 for rarely used keys. D6 indicates if it is a key-press or release event except when D5:D0 indicate key 63 or key 62. Reading the key-scan FIFO clears the interrupt INT depending on the setting of bit D5 in the configuration register (0x01). Configuration Register (0x01) The configuration register controls the I2C bus timeout feature, enables key release detection, enables autowake, and determines how INT should be deasserted. By writing to bit D7, you can put the MAX7359 into sleep mode or operating mode, however, autosleep and autowake, when enabled, also change the status of this bit (Table 4).
MAX7359
_____________________Initial Power-Up
On power-up, all control registers are set to power-up values and the MAX7359 is in sleep mode (Table 2).
Registers Description
Keys FIFO Register (0x00) The keys FIFO register contains the information pertaining to the status of the keys FIFO, as well as the key events that have been debounced (Table 3). Bits D0 to
Table 1. Key-Switch Mapping
PIN ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 COL0 KEY 0 KEY 1 KEY 2 KEY 3 KEY 4 KEY 5 KEY 6 KEY 7 COL1 KEY 8 KEY 9 KEY 10 KEY 11 KEY 12 KEY 13 KEY 14 KEY 15 COL2/PORT2 COL3/PORT3 COL4/PORT4 COL5/PORT5 COL6/PORT6 COL7/PORT7 KEY 16 KEY 17 KEY 18 KEY 19 KEY 20 KEY 21 KEY 22 KEY 23 KEY 24 KEY 25 KEY 26 KEY 27 KEY 28 KEY 29 KEY 30 KEY 31 KEY 32 KEY 33 KEY 34 KEY 35 KEY 36 KEY 37 KEY 38 KEY 39 KEY 40 KEY 41 KEY 42 KEY 43 KEY 44 KEY 45 KEY 46 KEY 47 KEY 48 KEY 49 KEY 50 KEY 51 KEY 52 KEY 53 KEY 54 KEY 55 KEY 56 KEY 57 KEY 58 KEY 59 KEY 60 KEY 61 KEY 62 KEY 63
Table 2. Register Address Map and Power-Up Condition
ADDRESS CODE (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 READ/WRITE Read only R/W R/W R/W R/W R/W R/W POWER-UP VALUE (hex) 0x3F 0x0A 0xFF 0x00 0xFE 0x00 0x07 REGISTER FUNCTION Keys FIFO Configuration Debounce Interrupt Ports Key repeat Sleep DESCRIPTION Read FIFO key scan data out Power down, key release enable, autowakeup, and I2C timeout enable Key debounce time setting and GPO enable INT frequency setting Ports 2-7 and INT GPO control Delay and frequency for key repeat Idle time to autosleep
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
Table 3. Keys FIFO Register Format (0x00)
SPECIAL FUNCTION The key number indicated by D5:D0 is a key event. D7 is always for a key press of key 62 and key 63. When D7 is 0, the key read is the last data in the FIFO. When D7 is 1, there is more data in the FIFO. When D6 is 1, key data read from FIFO is a key release. When D6 is 0, key data read from FIFO is a key press. FIFO is empty. FIFO is overflow. Continue to read data in FIFO. Key 63 is pressed. Read one more time to determine whether there is more data in FIFO. Key 63 is released. Read one more time to determine whether there is more data in FIFO. Key repeat. Indicates the last data in FIFO. Key repeat. Indicates more data in FIFO. Key 62 is pressed. Read one more time to determine whether there is more data in FIFO. Key 62 is released. Read one more time to determine whether there is more data in FIFO. KEYS FIFO REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0
FIFO empty flag
Key release flag
X
X
X
X
X
X
0 0 1 1
0 1 0 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 0 0
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
Table 4. Configuration Register Format (0x01)
REGISTER BIT DESCRIPTION VALUE 0 D7 Sleep 1 Operating mode Sleep mode FUNCTION I2C write, autosleep and autowakeup all can change this bit. This bit can be read back by I2C any time for current status. DEFAULT VALUE
0
D6
Reserved
0 0
This bit must always be 0. Improper operation may result by writing a 1 to this location. Clear when FIFO empty Clear after host read. In this mode, I2C should read FIFO until interrupt condition removed, or further INT may be lost. This bit must always be 0. Improper operation may result by writing a 1 to this location. Disable Enable This bit must always be 0. Improper operation results by writing a 1 to this location. Disable Key press wakeup enable I2C timeout enabled I2C timeout disabled
0
D5
INTERRUPT
1
0
D4 D3 D2 D1 D0
Reserved Key release enable Reserved Wakeup Timeout enable
0 0 1 0 0 1 0 1
0 1 0 1 0
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
Debounce Register (0x02) The debounce register sets the time for each debounce cycle, as well as setting whether the GPO ports are enabled or disabled. Bits D0 through D4 set the debounce time in increments of 1ms starting at 9ms
and ending at 40ms (Table 5). Bits D5 through D7 set which of the GPO ports is enabled. Note the GPO ports can be enabled only in the combinations shown in Table 5, from all disabled to all enabled.
Table 5. Debounce Register Format (0x02)
REGISTER DATA REGISTER DESCRIPTION Debounce time is 9ms Debounce time is 10ms Debounce time is 11ms Debounce time is 12ms . . . Debounce time is 37ms Debounce time is 38ms Debounce time is 39ms Debounce time is 40ms GPO ports disabled (full key-scan functionality) GPO port 7 enabled GPO ports 7 and 6 enabled GPO ports 7, 6, and 5 enabled GPO ports 7, 6, 5, and 4 enabled GPO ports 7, 6, 5, 4, and 3 enabled GPO ports 7, 6, 5, 4, 3, and 2 enabled Power-up default setting X X X X 0 0 0 0 1 1 1 1 X X X X 0 0 1 1 0 0 1 1 X X X X 0 1 0 1 0 1 X 1 1 1 1 1 X X X X X X X 1 1 1 1 1 X X X X X X X 1 1 1 1 1 X X X X X X X 1 0 0 1 1 X X X X X X X 1 0 1 0 1 X X X X X X X 1 D7 X X X X D6 X X X X D5 X X X X D4 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1 PORTS ENABLE DEBOUNCE TIME
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO
Interrupt Register (0x03) The interrupt register contains information related to the settings of the interrupt request function, as well as the status of the INT output, which can also be configured as a GPO. If bits D0 through D7 are set to 0x00, the INT output is configured as a GPO that is controlled by bit D1 in the port register. There are two types of interrupts, the FIFO based-interrupt and time-based interrupt. The timebased interrupt can be configured to assert INT after a number of debounce cycles. By setting bits D0 through
D4 to an appropriate value, the interrupt can be asserted at the end of the selected number of debounce cycles following a key event (Table 6). This number ranges from 1 to 31 debounce cycles. The FIFO based interrupt can be configured to assert INT when there are between 4 through 16 key events stored in the FIFO. Bits D7 through D5 set the FIFO based interrupt. Both interrupts can be configured simultaneously and INT asserts depending on which condition is met first. INT deasserts depending on the status of bit D5 in the configuration register.
MAX7359
Table 6. Interrupt Register Format (0x03)
REGISTER DATA REGISTER DESCRIPTION INT used as GPO FIFO based INT disabled INT asserts every debounce cycles INT asserts every 2 debounce cycles D7 0 0 0 0 . . . INT asserts every 29 debounce INT asserts every 30 debounce INT asserts every 31 debounce Time based INT disabled INT asserts when FIFO has 2 key events INT asserts when FIFO has 4 key events INT asserts when FIFO has 6 key events 0 0 0 . . . INT asserts when FIFO has 16 key events Both time base and FIFO based interrupts active Power-up default setting 0 1 1 Not all zero 0 0 0 0 1 0 0 0 Not all zero 0 0 0 0 0 0 0 0 0 0 0 Not all zero 0 1 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 D6 0 0 0 0 D5 0 0 0 0 0 0 0 0 D4 0 D3 0 D2 0 Not all zero 0 0 0 1 1 0 D1 0 D0 0 FIFO-BASED INT TIME-BASED INT
Ports Register (0x04) The ports register sets the values of ports 2 through 7 and the INT port when configured as open-drain GPOs. The settings in this register are ignored for ports not configured as GPOs, and a read from this register returns the values stored in the register (Table 7). Autorepeat Register (0x05) The MAX7359 autorepeat feature notifies the host that at least one key has been pressed for a continuous period of time. The autorepeat register enables or disables this feature, sets the time delay after the last key event before the key repeat code (0x7E) is entered into the FIFO, and
sets the frequency at which the key repeat code is entered into the FIFO thereafter. Bit D7 specifies whether the autorepeat function is enabled with 0 denoting autorepeat disabled and 1 denoting autorepeat enabled. Bits D0 through D3 specify the autorepeat delay in terms of debounce cycles ranging from eight debounce cycles to 128 debounce cycles (Table 8). Bits D4 through D6 specify the autorepeat rate or frequency ranging from 4 to 32 debounce cycles. When autorepeat is enabled, holding the key pressed results in a key repeat event that is denoted by 0x7E. The key being pressed does not show up again in the FIFO.
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
Table 7. Ports Register Format (0x04)
REGISTER BIT D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION PORT 7 Control PORT 6 Control PORT 5 Control PORT 4 Control PORT 3 Control PORT 2 Control INT Port Control Reserved VALUE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 FUNCTION Clear port 7 low Set port 7 high (high impedance) Clear port 6 low Set port 6 high (high impedance) Clear port 5 low Set port 5 high (high impedance) Clear port 4 low Set port 4 high (high impedance) Clear port 3 low Set port 3 high (high impedance) Clear port 2 low Set port 2 high (high impedance) Clear port INT low Set port INT high (high impedance) -- DEFAULT VALUE 1 1 1 1 1 1 1 0
Table 8. Autorepeat Register Format (0x05)
REGISTER DATA REGISTER DESCRIPTION D7 ENABLE Autorepeat is disabled Autorepeat is enabled Key-switch autorepeat delay is 8 debounce cycles Key-switch autorepeat delay is 16 debounce cycles Key-switch autorepeat delay is 24 debounce cycles . . . Key-switch autorepeat delay is 112 debounce cycles Key-switch autorepeat delay is 120 debounce cycles Key-switch autorepeat delay is 128 debounce cycles Key-switch autorepeat frequency is 4 debounce cycles Key-switch autorepeat frequency is 8 debounce cycles Key-switch autorepeat frequency is 12 debounce cycles . . . Key switch autorepeat frequency is 32 debounce cycles Power-up default setting 1 0 1 0 1 0 1 0 X 0 X 0 X 0 X 0 1 1 1 1 1 1 X X X 0 0 0 X X X 0 0 1 X X X 0 1 0 1 1 1 X X X 1 1 1 X X X 0 1 1 X X X 1 0 1 X X X 0 1 1 1 1 D6 D5 D4 D3 D2 D1 D0 AUTOREPEAT RATE X X X X X X X X X X X X AUTOREPEAT DELAY X 0 0 0 X 0 0 0 X 0 0 1 X 0 1 0
AUTOREPEAT RATE
AUTOREPEAT DELAY
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO
Only one autorepeat code is entered into the FIFO, regardless of the number of keys pressed. The autorepeat code continues to be entered in the FIFO at the frequency set by the bits D4-D1 until another key event is recorded. Following the key-release event, if any keys are still pressed, the MAX7359 restarts the autorepeat sequence.
Serial Addressing
The MAX7359 operates as a slave that sends and receives data through an I2C-compatible 2-wire interface. The interface uses a serial-data line (SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX7359 and generates the SCL clock that synchronizes the data transfer. The MAX7359's SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on SDA. The MAX7359's SCL line operates only as an input. A pullup resistor is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START condition (Figure 2) sent by a master, followed by the MAX7359 7-bit slave address plus R/W bit, a register address byte, 1 or more data bytes, and finally a STOP condition.
MAX7359
Autosleep Register (0x06) Autosleep puts the MAX7359 in sleep mode to draw minimal current. When enabled, the MAX7359 enters sleep mode if no keys are pressed for the autosleep time (Table 9).
Sleep Mode
In sleep mode, the MAX7359 draws minimal current. Switch matrix current sources are turned off and pulled up to VCC. Writing a 0 to D7 in the configuration register (0x01) puts the device in sleep mode. Writing a 1 to D7 or a key press, when the part is programmed to autowake, can take the MAX7359 out of sleep mode. Bit D7 in the configuration register gives the sleep mode status and can be read anytime. The FIFO data is maintained while in sleep mode.
Autowake
Key presses initiate autowake and the MAX7359 goes into operating mode. Key presses that autowake the MAX7359 are not lost. When a key is pressed while the MAX7359 is in sleep mode, all analog circuitry, including switch matrix current sources, turn on in 2ms. The initial key needs to be pressed for 2ms plus the debounce time to be stored in the FIFO. Autowakeup can be disabled by writing a 0 to D1 in the configuration register (0x01).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission.
Bit Transfer
One data bit is transferred during each clock pulse (Figure 3). The data on SDA must remain stable while SCL is high.
Serial Interface
Figure 1 shows the 2-wire serial interface timing details.
Table 9. Autosleep Register Format (0x06)
REGISTER AUTOSLEEP REGISTER No Autosleep Autosleep for (ms) 8192 4096 2048 1024 512 256 256 Power-up default settings 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 RESERVED D7 0 D6 0 D5 0 D4 0 D3 0 REGISTER DATA AUTOSHUTDOWN TIME D2 0 D1 0 D0 0
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
tR SDA tSU, DAT tLOW tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION tHD, DAT
tF tF,TX tBUF
tSU, STA
tHD, STA tSU, STO
SCL
STOP CONDITION
START CONDITION
Figure 1. 2-Wire Serial Interface Timing Details
SDA
SCL S START CONDITION P STOP CONDITION
Figure 2. Start and Stop Conditions
SDA
SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 3. Bit Transfer
14
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 4), which the recipient uses to handshake receipt of each byte of data. Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, so the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX7359, the MAX7359 generates the acknowledge bit because the MAX7359 is the recipient. When the MAX7359 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. The MAX7359 monitors the bus continuously, waiting for a START condition followed by its slave address. When the MAX7359 recognizes its slave address, it acknowledges and is then ready for continued communication.
MAX7359 MAX7359
Bus Timeout
The MAX7359 features a 20ms minimum bus timeout on the 2-wire serial interface, largely to prevent the MAX7359 from holding the SDA I/O low during a read transaction if the SCL hangs for any reason before a serial transaction has been completed. Bus timeout operates by causing the MAX7359 to internally terminate a serial transaction, either read or write, if SCL low exceeds 20ms. After a bus timeout, the MAX7359 waits for a valid START condition before responding to a consecutive transmission. This feature can be enabled or disabled under user control by writing to the configuration register (Table 4).
Slave Addresses
The MAX7359 has a 7-bit long slave address (Figure 5). The bit following a 7-bit slave address is the R/W bit, which is low for a write command and high for a read command. The first 4 bits (MSBs) of the MAX7359 slave address are always 0111. Slave address bits A3, A2, and A1 correspond, by the matrix in Table 10, to the states of the device address input AD0, and A0 corresponds to the R/W bit. The AD0 input can be connected to any of four signals: GND, VCC, SDA, or SCL, giving four possible slave address pairs, allowing up to four MAX7359 devices to share the bus. Because SDA and SCL are dynamic signals, care must be taken to ensure that AD0 transitions no sooner than the signals on the SDA and SCL pins.
START CONDITION
Table 10. 2-Wire Interface Address Map
PIN ADO GND VCC SDA SCL DEVICE ADDRESS A7 0 0 0 0 A6 1 1 1 1 A5 1 1 1 1 A4 1 1 1 1 A3 0 0 1 1 A2 0 1 0 1 A1 0 0 0 1 A0 R/W R/W R/W R/W
CLOCK PULSE FOR ACKNOWLEDGE 1 2 8 9
SCL
SDA BY TRANSMITTER SDA BY RECEIVER S
Figure 4. Acknowledge
SDA SCL
0 MSB
1
1
1
A3
A2
A1 LSB
R/W
ACK
Figure 5. Slave Address
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15
2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
COMMAND BYTE IS STORED ON RECEIPT OF ACKNOWLEDGE CONDITION ACKNOWLEDGE FROM MAX7359 S SLAVE ADDRESS R/W 0 A D7 D6 D5 D4 D3 D2 D1 D0
COMMAND BYTE ACKNOWLEDGE FROM MAX7359
A
P
Figure 6. Command Byte Received
ACKNOWLEDGE FROM MAX7359 D7 ACKNOWLEDGE FROM MAX7359 S SLAVE ADDRESS R/W 0 A COMMAND BYTE A DATA BYTE 1 BYTE AUTOINCREMENT COMMAND BYTE ADDRESS A P D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 ACKNOWLEDGE FROM MAX7359 D4 D3 D2 D1 D0
Figure 7. Command and Single Data Byte Received
Message Format for Writing the Key-Scan Controller
A write to the MAX7359 comprises the transmission of the slave address with the R/W bit set to zero, followed by at least 1 byte of information. The first byte of information is the command byte. The command byte determines which register of the MAX7359 is to be written by the next byte, if received. If a STOP condition is detected after the command byte is received, the MAX7359 takes no further action (Figure 6) beyond storing the command byte. Any bytes received after the command byte are data bytes. The first data byte goes into the internal register of the MAX7359 selected by the command byte (Figure 7). If multiple data bytes are transmitted before a STOP condition is detected, these bytes are generally stored in subsequent MAX7359 internal registers (Table 7) because the command byte address generally autoincrements (Table 11).
Table 11. Autoincrement Rules
REGISTER FUNCTION Keys FIFO Autoshutdown All other ADDRESS CODE (hex) 0x00 0x06 0x01 thru 0x05 AUTOINCREMENT ADDRESS (hex) 0x00 0x00 Addr + 0x01
write (Figure 6). The master can now read n consecutive bytes from the MAX7359, with the first data byte being read from the register addressed by the initialized command byte. When performing read-after-write verification, remember to reset the command byte's address because the stored command byte address is generally autoincremented after the write (Figure 8, Table 11).
Operation with Multiple Masters
If the MAX7359 is operated on a 2-wire interface with multiple masters, a master reading the MAX7359 should use a repeated start between the write that sets the MAX7359's address pointer, and the read(s) that takes the data from the location(s). This is because it is possible for master 2 to take over the bus after master 1 has set up the MAX7359's address pointer but before master 1 has read the data. If master 2 subsequently resets the MAX7359's address pointer, master 1's read may be from an unexpected location.
Message Format for Reading the Key-Scan Controller
The MAX7359 is read using the MAX7359's internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. The pointer generally autoincrements after each data byte is read using the same rules as for a write (Table 11). Thus, a read is initiated by first configuring the MAX7359's command byte by performing a
16
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359 MAX7359
ACKNOWLEDGE FROM MAX7359 D7 ACKNOWLEDGE FROM MAX7359 S SLAVE ADDRESS R/W 0 A COMMAND BYTE A DATA BYTE N BYTES AUTOINCREMENT COMMAND BYTE ADDRESS A P D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 ACKNOWLEDGE FROM MAX73459 D4 D3 D2 D1 D0
Figure 8. N Data Bytes Received
Command Address Autoincrementing
Address autoincrementing allows the MAX7359 to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. The command address stored in the MAX7359 generally increments after each data byte is written or read (Table 11). Autoincrement only works when doing a multiburst read or write.
three keys are not wired in positions that define the vertices of a rectangle (Figure 10). There is no limit on the number of keys that can be pressed simultaneously as long as the keys do not generate ghost key events and FIFO is not full.
Applications Information
Ghost-Key Elimination
Ghost keys are a phenomenon inherent with key-switch matrices. When three switches located at the corners of a matrix rectangle are pressed simultaneously, the switch that is located at the last corner of the rectangle (the ghost key) also appears to be pressed. This occurs because the potentials at the two sides of the ghost-key switch are identical due to the other three connections-- the switch is electrically shorted by the combination of the other three switches (Figure 9). Because the key appears to be pressed electrically, it is impossible to detect which of the four keys is the ghost key. The MAX7359 employs a proprietary scheme that detects any three-key combination that generates a fourth ghost key, and does not report the third key that causes a ghost key event. This means that although ghost keys are never reported, many combinations of three keys are effectively ignored when pressed at the same time. Applications requiring three-key combinations (such as ) must ensure that the
Low-EMI Operation The MAX7359 uses two techniques to minimize EMI radiating from the key-switch wiring. First, the voltage across the switch matrix never exceeds 0.55V when not in sleep mode, irrespective of supply voltage VCC. This reduces the voltage swing at any node when a switch is pressed to 0.55V maximum. Second, the keys are not dynamically scanned, which would cause the keyswitch wiring to continuously radiate interference. Instead, the keys are monitored for current draw (only occurs when pressed), and debounce circuitry only operates when one or more keys are actually pressed.
Power-Supply Considerations
The MAX7359 operates with a 1.62V to 3.6V powersupply voltage. Bypass the power supply to GND with a 0.047F or higher ceramic capacitor as close as possible to the device.
Switch On-Resistance
The MAX7359 is designed to be insensitive to resistance either in the key switches or the switch routing to and from the appropriate COLx and ROWx up to 5k. These controllers are therefore compatible with lowcost membrane and conductive carbon switches.
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17
2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
REGULAR KEY-PRESS EVENT GHOST-KEY EVENT EXAMPLES OF VALID THREE-KEY COMBINATIONS
KEY-SWITCH MATRIX
KEY-SWITCH MATRIX
KEY-SWITCH MATRIX
Figure 9. Ghost-Key Phenomenon
Figure 10. Valid Three-Key Combinations
Chip Information
PROCESS: BiCMOS
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO
Typical Application Circuit
MAX7359 MAX7359
3.3V
3.3V
1.8V COL5/PORT5 VCC COL4/PORT4 COL3/PORT3 COL2/PORT2 COL6/PORT6 COL1 COL7/PORT7 AD0 COL0 ROW0 ROW1 KEY 3 KEY 11 KEY 19 KEY 27 KEY 35 KEY 43 KEY 2 KEY 10 KEY 18 KEY 26 KEY 34 KEY 42 KEY 1 KEY 9 KEY 17 KEY 25 KEY 33 KEY 41 KEY 0 KEY 8 KEY 16 KEY 24 KEY 32 KEY 40
MAX7359
5V
ROW2 ROW3
VCC C SCL SDA INT GND GND SCL SDA INT
KEY 4
KEY 12
KEY 20
KEY 28
KEY 36
KEY 44
ROW4 ROW5 KEY 5 ROW6 ROW7 KEY 6 KEY 14 KEY 22 KEY 30 KEY 38 KEY 46 KEY 13 KEY 21 KEY 29 KEY 37 KEY 45
KEY 7
KEY 15
KEY 23
KEY 31
KEY 39
KEY 47
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19
2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
Pin Configuration
TOP VIEW
AD0 COL0 13 12 COL1 11 COL2/PORT2 10 COL5/PORT5 SDA SCL GND 15 I.C. 14
18 INT 19 VCC 20 N.C. 21 COL7/PORT7 22 ROW0 23 ROW1 24 + 1 ROW2
17
16
MAX7359
EP* 2 ROW3 3 COL3/PORT3 4 COL4/PORT4 5 ROW4 6 ROW5
9 8 7
COL6/PORT6 ROW7 ROW6
TQFN-EP
*EP = EXPOSED PADDLE
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2-Wire Interfaced Low-EMI Key Switch Controller/GPO
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX7359 MAX7359
______________________________________________________________________________________
24L THIN QFN.EPS
21
2-Wire Interfaced Low-EMI Key Switch Controller/GPO MAX7359
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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